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LCJ/JH 9/22/05 (P1)
19-2729; Rev 1; 8/05
KIT ATION EVALU ILABLE AVA
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
General Description
The MAX1536 constant-off-time, pulse-width-modulated (PWM) step-down DC-to-DC converter is ideal for use in +5.0V and +3.3V to low voltages for notebook and subnotebook computers. The MAX1536 features an internal PMOS power switch and internal synchronous rectification for high efficiency and reduced component count. No external Schottky diode is required across the internal synchronous rectifier switch. The internal 54m PMOS power switch and 47m NMOS synchronous-rectifier switch easily deliver continuous load currents up to 3.6A. The MAX1536 produces dynamically adjustable output voltages for chipsets and graphics processor cores using a logic-level control signal. The MAX1536 achieves efficiencies as high as 96%. The MAX1536 uses a unique current-mode, constant-offtime, PWM control scheme. It has selectable Idle ModeTM to maintain high efficiency during light-load operation, or fixed-PWM mode for low output ripple. The programmable constant-off-time architecture allows a wide range of switching frequencies up to 1.4MHz, optimizing performance trade-offs between efficiency, output switching noise, component size, and cost. The MAX1536 features a digital soft-start to limit surge currents during startup, a 100% duty-cycle mode for lowdropout operation, and a low-power shutdown mode that disconnects the input from the output and reduces supply current below 1A. The MAX1536 is available in a 28-pin thin QFN package with an exposed backside pad.
Features
Dynamically Selectable Output Voltage from +0.7V to VIN Internal PMOS/NMOS Switches 54m/47m On-Resistance at VIN = +4.5V 63m/53m On-Resistance at VIN = +3.0V +3.0V to +5.5V Input Voltage Range 1.4MHz Maximum Switching Frequency 2V 0.75% Reference Output Constant-Off-Time PWM Operation Selectable Idle Mode/PWM Operation at Light Loads 100% Duty Factor in Dropout Digital Soft-Start Inrush Current Limiting <1A Typical Shutdown Supply Current <750A Quiescent Supply Current Thermal Shutdown 1% VOUT Accuracy Over Line and Load External Reference Input Power-Good Window Comparator Selectable Power-Good Blanking Time During Output-Voltage Transition
MAX1536
Ordering Information
PART MAX1536ETI MAX1536ETI+ TEMP RANGE -40oC to +85oC -40oC to +85oC PIN-PACKAGE 28 Thin QFN 5mm x 5mm 28 Thin QFN 5mm x 5mm
________________________Applications
Chipset/Graphics Cores with Dual-Supply Voltages Active Termination Buses Notebook Computers DDR Memory Termination
+Denotes lead-free package.
Pin Configuration
FBLANK PGOOD VCC LX IN IN
Minimal Operating Circuit
VIN +3.0V TO +5.5V VOUT +0.7V TO VIN IN LX FB VCC SHDN COMP PGND AGND
TOP VIEW
21
PGND PGND LX N.C. LX PGND PGND
20
19
18
17
16
15 14 13 12 11
REF REFIN OD OD GATE TOFF N.C.
22 23 24 25
MAX1536
26 27 28 1
LX EXPOSED PADDLE
AGND
10 9 8 6
FB
MAX1536
REF
PGOOD TOFF SKIP REFIN
2
IN
3
IN
4
SHDN
5
SKIP
7
COMP
THIN QFN
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
Idle Mode is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
ABSOLUTE MAXIMUM RATINGS
VCC, IN, SHDN, SKIP to AGND ................................-0.3V to +6V OD, OD, GATE, PGOOD to AGND...........................-0.3V to +6V COMP, FB, REF to AGND.........................................-0.3V to +6V TOFF, REFIN, FBLANK to AGND .............................-0.3V to +6V IN to VCC ...............................................................-0.3V to +0.3V PGND to AGND .................................................... -0.3V to +0.3V LX to PGND ................................................ -0.3V to (VIN + 0.3V) LX Current (Note 1).............................................................5.7A REF Short Circuit to AGND.........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derated 20.8mW/C above +70C; part mounted on 1in2 of 1oz copper) .........................1667mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX has clamp diodes to PGND and IN. Thermal limits dictate the maximum continuous current through these diodes.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VCC = V SHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWM CONTROLLER Input Voltage Output Adjust Range Feedback Voltage Accuracy Feedback Load Regulation FB Input Bias Current Dropout PMOS Switch On-Resistance NMOS Switch On-Resistance Maximum Output Current Current-Limit Threshold Idle Mode Current Threshold Zero-Cross Current Threshold Switching Frequency Off-Time Extended Off-Time On-Time Soft-Start Time Quiescent Supply Current ICC + IIN tON fSW tOFF IFB VDO RPMOS RNMOS VIN, VCC VOUT VFB VREFIN VCC = VIN = +3.0V to +5.5V, ILOAD = 0 TA = +25C to +85C TA = 0C to +85C 3.0 VREFIN -3 -4 0 0 0.3 -50 189 54 63 47 53 4.0 0.21 4.8 0.60 200 1.4 RTOFF = 30.1k VFB 0.3 x VREFIN VFB < 0.3 x VREFIN (Note 2) (Note 3) SKIP = AGND, VFB = 1.01 x VREFIN 0.3 3 x 256 350 750 RTOFF = 110k RTOFF = 499k 0.24 0.85 3.8 0.30 1.00 4.5 4 x tOFF 0.37 1.15 5.2 s s Cycles A s +50 330 90 110 80 90 3.6 5.5 1.00 5.5 VIN +3 +4 V V mV % nA mV m m A A A mA MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
ILOAD = 0 to 3.5A, VCC = VIN = +3.0V to +5.5V, SKIP = VCC VFB = 1.01 x VREFIN VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND VCC = VIN = +4.5V, ILOAD = 0.5A VCC = VIN = +3.0V, ILOAD = 0.5A VCC = VIN = +4.5V, ILOAD = 0.5A VCC = VIN = +3.0V, ILOAD = 0.5A (Note 3) SKIP = AGND SKIP = AGND (Note 2)
IOUT(RMS) (Note 2) ILIMIT
2
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VCC = V SHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL ICC + IIN Shutdown Supply Currents IIN ILX REFERENCE REF Voltage REF Load Regulation REFIN Input Voltage Range REFIN Input Bias Current FAULT DETECTION Thermal Shutdown Undervoltage Lockout Threshold PGOOD Lower Trip Threshold PGOOD Upper Trip Threshold PGOOD Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current Fault Blanking Time INPUTS AND OUTPUTS V SHDN, V SKIP, VGATE SHDN, SKIP, GATE, VIN = VCC = +3.3V, rising edge, hysteresis = 100mV SHDN, SKIP, GATE, VIN = VCC = +5.0V, rising edge, hysteresis = 100mV SHDN, SKIP, GATE FBLANK = VCC FBLANK Logic Thresholds VFBLANK FBLANK = REF FBLANK = open FBLANK = AGND FBLANK Input Current OD On-Resistance OD Leakage Current OD On-Resistance OD Leakage Current R OD IFBLANK ROD FBLANK forced to AGND or VCC GATE = VCC GATE = AGND, VOD = +5.5V GATE = AGND GATE = VCC, V OD = +5.5V -50 -50 10 -5 10 0.9 1.15 -0.5 VCC - 0.2 1.8 0.8 2.2 1.2 0.2 +5 25 +50 25 +50 A nA nA V 1.3 1.55 1.6 V 1.95 +0.5 A tFBLANK tPGOOD TSHDN Rising, hysteresis = 15C VCC and VIN rising, hysteresis 60mV typical VCC - VREFIN, VCC rising, hysteresis 60mV typical VCC - VFB, VCC rising, hysteresis 60mV typical No load, falling edge, hysteresis = 1% (Note 4) No load, rising edge, hysteresis = 1% (Note 4) FB forced 2% beyond PGOOD trip threshold ISINK = 1mA High-impedance state, forced to +5.5V FBLANK = VCC FBLANK = open or AGND FBLANK = REF 112 75 37 150 100 50 -12.5 +8.0 2.4 165 2.6 0.9 0.9 -10 +10 5 0.1 1 188 125 63 s 2.8 1.35 1.35 -8.0 +12.5 % % s V A V C VREFIN IREFIN VREF VCC = VIN = +3.0V to +5.5V IREF = -1A to +50A VCC = VIN = +3.0V to +5.5V, VCC > VREFIN + 1.35V VREFIN = 1.5V, VFB = 1.01 x VREFIN 0.7 -50 1.985 2.000 2.015 10 2.0 +50 V mV V nA CONDITIONS SHDN = AGND; current into VCC and IN; LX = 0 or +3.3V SHDN = AGND; current into IN; LX = 0 SHDN = AGND; current into LX; LX = +3.3V MIN TYP 0.2 0.2 0.1 MAX 20 20 20 A UNITS
MAX1536
Logic Input Threshold
Logic Input Current
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3
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VCC = V SHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER PWM CONTROLLER Input Voltage Feedback Voltage Accuracy FB Input Bias Current Dropout PMOS Switch On-Resistance NMOS Switch On-Resistance Maximum Output Current Current-Limit Threshold Idle Mode Current Threshold Switching Frequency Off-Time On-Time Quiescent Supply Current fSW tOFF tON ICC + IIN ICC + IIN Shutdown Supply Currents IIN ILX REFERENCE REF Voltage REFIN Input Voltage Range FAULT DETECTION PGOOD Lower Trip Threshold PGOOD Upper Trip Threshold No load, falling edge, hysteresis = 1% (Note 4) No load, rising edge, hysteresis = 1% (Note 4) -12.5 +8 -8 +12.5 % % VREF VREFIN VCC = VIN = +3.0V to +5.5V VCC = VIN = +3.0V to +5.5V, VCC > VREFIN + 1.35V 1.98 0.7 2.02 2.0 V V VIN, VCC VFB VREFIN IFB VDO RPMOS RNMOS VCC = VIN = +3.0V to +5.5V, ILOAD = 0 VFB = 1.01 x VREFIN VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND VCC = VIN = +4.5V, ILOAD = 0.5A VCC = VIN = +3.0V, ILOAD = 0.5A VCC = VIN = +4.5V, ILOAD = 0.5A VCC = VIN = +3.0V, ILOAD = 0.5A (Note 3) SKIP = AGND (Note 2) RTOFF = 30.1k VFB 0.3 x VREFIN (Note 2) SKIP = AGND, VFB = 1.01 x VREFIN SHDN = AGND; current into VCC and IN; LX = 0 or +3.3V SHDN = AGND; current into IN; LX = 0 SHDN = AGND; current into LX; LX = +3.3V RTOFF = 110k RTOFF = 499k 0.24 0.85 3.8 0.3 750 20 20 20 A 4.0 0.21 3.0 -4 -50 5.5 +4 +50 330 90 110 80 90 3.6 5.7 1.00 1.4 0.37 1.15 5.2 s A s V mV nA mV m m A A A MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
IOUT(RMS) (Note 2) ILIMIT
4
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VCC = V SHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER INPUTS AND OUTPUTS V SHDN, V SKIP, V GATE SHDN, SKIP, GATE, VIN = VCC = +3.3V, rising edge, hysteresis = 100mV SHDN, SKIP, GATE, VIN = VCC = +5.0V, rising edge, hysteresis = 100mV FBLANK = VCC FBLANK Logic Thresholds VFBLANK FBLANK = REF FBLANK = open FBLANK = AGND OD On-Resistance OD On-Resistance ROD R OD GATE = VCC GATE = AGND 0.9 1.15 VCC - 0.2 1.8 0.8 2.2 1.2 0.2 25 25 V 1.6 V 1.95 SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1536
Logic Input Threshold
Note 2: Guaranteed by design and not production tested. Note 3: To limit input surge currents, the current-limit threshold is set to 25% of its final value (25% x 4.8A = 1.2A) when the MAX1536 is enabled or powered up. The current-limit threshold is increased by 25% every 256 LX cycles. The current-limit threshold is at its final level of 4.8A after 768 LX cycles. See the Internal Soft-Start Circuit section. Note 4: The upper and lower PGOOD thresholds are expressed as a ratio of VFB with respect to VREFIN.
VFB - VREFIN x100% VREFIN
Note 5: Specifications to -40C are guaranteed by design and are not production tested.
Typical Operating Characteristics
(MAX1536 Circuit of Figure 1, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT (VIN = 5V, L = 1.5H)
MAX1536 toc01
OUTPUT VOLTAGE vs. OUTPUT CURRENT (VIN = 5V, L = 1.5H)
RTOFF = 93.1k 1.804 OUTPUT VOLTAGE (V) 1.802 1.800 1.798 1.796 1.794 PWM MODE IDLE MODE
MAX1536 toc02
EFFICIENCY vs. OUTPUT CURRENT (VIN = 3.3V, L = 1.2H)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VOUT = 2.5V RTOFF = 42.2k VOUT = 1.8V RTOFF = 75k VOUT = 0.7V RTOFF = 165k PWM MODE IDLE MODE 0.001 0.01 0.1 1 10
MAX1536 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001
PWM MODE IDLE MODE
1.806
100
VOUT = 2.5V RTOFF = 54.9k VOUT = 1.8V RTOFF = 93.1k VOUT = 0.7V RTOFF = 200k
0.01
0.1
1
10
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Typical Operating Characteristics (continued)
(MAX1536 Circuit of Figure 1, TA = +25C, unless otherwise noted.)
OUTPUT VOLTAGE vs. OUTPUT CURRENT (VIN = 3.3V, L = 1.2H)
MAX1536 toc04
EFFICIENCY vs. OUTPUT CURRENT (VOUT = 1.8V, fSW = 300kHz)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 VIN = 3.3V L = 2.2H RTOFF = 147k VIN = 5V L = 3.3H RTOFF = 221k PWM MODE IDLE MODE 0.001 0.01 0.1 1 10
MAX1536 toc05
1.806 RTOFF = 75k 1.804 OUTPUT VOLTAGE (V) 1.802 1.800 1.798 1.796 1.794 0.001 0.01 0.1 1 PWM MODE IDLE MODE
100
0 10 OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT (VIN = 3.3V, VOUT = 1.8V)
MAX1536 toc06
SWITCHING FREQUENCY vs. OUTPUT CURRENT
900 800 700 fSW (kHz) 600 500 400 VIN = 3.3V VIN = 5.0V VOUT = 1.8V
MAX1536 toc07
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001 0.01 0.1 L = 3.3H RTOFF = 178k fSW 250kHz L = 1.5H RTOFF = 85k fSW 500kHz L = 0.8H RTOFF = 41.2k fSW 1000kHz PWM MODE IDLE MODE 1
1000
300 200 100 0 10 0 1 2 3 4 5 PWM MODE IDLE MODE
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PWM MODE)
25 IIN
MAX1536 toc08
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (IDLE MODE)
1.0 1.05 1.04 0.8 1.03 1.02 ICC (mA)
MAX1536 toc09
VOUT = 1.8V 20
VOUT = 1.8V
350 345 340 335 ICC (A) 330
IIN (mA)
IIN (A)
15
0.6
1.01 1.00 0.99 0.98 ICC IIN
325 320 315 310 305 300
10 ICC 5
0.4
0.2
0.97 0.96
0 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 5.0
0
0.95 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 5.0
6
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
Typical Operating Characteristics (continued)
(MAX1536 Circuit of Figure 1, TA = +25C, unless otherwise noted.)
STARTUP AND SHUTDOWN (HEAVY LOAD)
MAX1536 toc10
MAX1536
STARTUP AND SHUTDOWN (LIGHT LOAD)
MAX1536 toc11
VSHDN 5V/div VPGOOD 5V/div
VSHDN 5V/div VPGOOD 5V/div
ILX 2A/div
ILX 1A/div VOUT 1V/div
VOUT 1V/div
400s/div VIN = 3.3V, VOUT = 1.8V, RLOAD = 0.5
400s/div VIN = 3.3V, VOUT = 1.8V, RLOAD = 3
LOAD-TRANSIENT RESPONSE (PWM MODE)
MAX1536 toc12
LOAD-TRANSIENT RESPONSE (IDLE MODE)
MAX1536 toc13
IOUT 2A/div
IOUT 2A/div
ILX 2A/div VOUT 50mV/div VLX 5V/div
ILX 2A/div VOUT 50mV/div VLX 5V/div
20s/div VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A
20s/div VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A
DYNAMIC OUTPUT-VOLTAGE TRANSITION (IDLE MODE)
MAX1536 toc14
REFERENCE VOLTAGE vs. TEMPERATURE
VIN = 3.3V 2.001 IREF = 0 IREF = 25A
MAX1536 toc15
VGATE 5V/div VLX 5V/div VREF (V) VOUT 200mV/div VREFIN 200mV/div 0 ILX 5A/div 20s/div VIN = 3.3V, VOUT = 1.5V TO 1.8V TO 1.5V, FBLANK = REF, ILOAD = 0.1A
2.002
2.000 1.999 1.998 1.997 1.996 -40 -15 10 35 60 85 TEMPERATURE (C)
IREF = 50A
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Pin Description
PIN 1, 21, 24, 26 2, 3, 19, 20 4 5 6 7 8, 25 9 NAME LX IN SHDN SKIP FB COMP N.C. TOFF FUNCTION Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier switch. Connect all LX pins together. Power Input. Power input for the internal PMOS switch. Connect all IN pins together. Shutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs. Drive SHDN high or connect to VCC for normal operation. Pulse-Skipping Control Input. Connect SKIP to VCC for low-noise, forced-PWM mode. Connect SKIP to AGND for high-efficiency Idle Mode. Feedback Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN). Integrator Compensation. Connect a 470pF capacitor from COMP to VCC for integrator compensation. See the Integrator Amplifier section. No Connection. Not internally connected. Connecting pin 25 to LX eases PC board layout. Off-Time Select Input. Sets the PMOS power switch off-time during constant off-time operation. Connect a resistor from TOFF to AGND to adjust the PMOS switch off-time. See the Programming the No-Load Switching Frequency and Off-Time section. Buffered OD and OD Control Input. A logic low on GATE forces OD low and OD high impedance. A logic high on GATE forces OD high impedance and OD low. Open-Drain Output. A logic low on GATE forces OD high impedance. A logic high on GATE forces OD low. Inverted Open-Drain Output. A logic low on GATE forces OD low. A logic high on GATE forces OD high impedance. External Reference Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN). +2.0V Reference Voltage Output. Bypass REF to AGND with a minimum capacitance of 0.22F. REF supplies up to 50A for external loads. The internal reference turns off in shutdown. Analog Ground. Connect backside pad to AGND. Analog Power Input. Power input to the internal analog circuitry. Bypass VCC with a 10 and 2.2F (min) lowpass filter (Figure 1).
10 11 12 13 14 15 16
GATE OD OD REFIN REF AGND VCC
17
Fault-Blanking Control Input. FBLANK is a four-level logic input that enables or disables fault blanking, and sets the minimum forced-PWM operation time (tFBLANK). Enabling fault blanking forces PGOOD high for the selected time period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for the duration of tFBLANK anytime GATE changes states. Connect FBLANK to the following pins to select tFBLANK and FBLANK fault blanking: VCC = 150s (typ), fault blanking enabled Open = 100s (typ), fault blanking enabled REF = 50s (typ), fault blanking enabled AGND = 100s (typ), fault blanking disabled Open-Drain Power-Good Output. PGOOD is low during soft-start, in shutdown, and when the output voltage is more than 10% (typ) above or below the normal regulation point. After the soft-start, PGOOD becomes high PGOOD impedance if the output is in regulation. PGOOD is blanked--forced into a high-impedance state--when FBLANK is enabled and a transition is detected on GATE. PGND Power Ground. Internally connected to the source of the internal NMOS synchronous-rectifier switch. Connect all PGND pins together.
18
22, 23, 27, 28
8
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
Standard Application Circuit
The MAX1536 standard application circuit (Figure 1) generates a dynamically adjustable output voltage typical of graphic processor core requirements. See Table 1 for component selections. Table 2 lists the component manufacturers. The NMOS switch remains on until the end of tOFF. Since either the NMOS or the PMOS switch is always on in PWM mode, the inductor current is continuous. Idle Mode (SKIP = AGND) Connect SKIP to AGND to allow the MAX1536 to automatically switch between high-efficiency Idle Mode under light loads and PWM mode under heavy loads. The transition from PWM mode to Idle Mode occurs when the load current is half the Idle Mode current threshold (600mA typ). In Idle Mode operation, the switching frequency is reduced to increase efficiency. The inductor current is discontinuous in this mode and the MAX1536 only initiates an LX switching cycle when VFB < VREFIN. When VFB falls below VREFIN, the PMOS switch turns on and remains on until output is in regulation and the current through the switch increases to the Idle Mode current threshold (600mA typ). When the PMOS switch turns off, the NMOS synchronous switch turns on and remains on until the current through the switch decreases to the zero-cross-current threshold of 200mA.
MAX1536
Detailed Description
The MAX1536 synchronous, current-mode, constantoff-time, PWM DC-to-DC converter steps down an input voltage (VIN) from +3.0V to +5.5V to an output voltage from +0.7V to VIN. The MAX1536 output delivers up to 3.6A of continuous current. An internal 54m PMOS power switch and an internal 47m NMOS synchronous rectifier switch improve efficiency, reduce component count, and eliminate the need for an external Schottky diode (Figure 2).
Modes of Operation
The MAX1536 has two modes of operation: constantoff-time PWM mode, and pulse-skipping Idle Mode. The logic level on the SKIP input and the current through the PMOS switch determine the MAX1536 mode of operation. Forced-PWM mode keeps the switching frequency relatively constant and is desirable in applications that must always keep the frequency of conducted and radiated emissions in a narrow band. Visit Maxim's website at www.maxim-ic.com for more information on how to control electromagnetic interference (EMI). Pulse-skipping Idle Mode has a dynamic switching frequency under light loads and is desirable in applications that require high efficiency at light loads. Forced-PWM Mode (SKIP = VCC) Connect SKIP to VCC to force the MAX1536 to operate in low-noise, constant-off-time PWM mode. Constantoff-time PWM architecture provides a relatively constant switching frequency (see the Frequency Variation with Output Current section). A single resistor (RTOFF) sets the PMOS power switch off-time that results in a switching frequency up to 1.4MHz optimizing performance trade-offs in efficiency, switching noise, component size, and cost. PWM mode regulates the output voltage by increasing the PMOS switch on-time to increase the amount of energy transferred to the load per cycle. At the end of each offtime, the PMOS switch turns on and remains on until the output is in regulation or the current through the switch increases to the 4.8A current limit. When the PMOS switch turns off, it remains off for the programmed offtime (tOFF), and the NMOS synchronous switch turns on.
100% Duty-Cycle Operation
When the input voltage drops near the output voltage, the LX duty cycle increases until the PMOS switch is on continuously. The dropout voltage in 100% duty cycle is the output current multiplied by the on-resistance of the internal PMOS switch and parasitic resistance in the inductor. The PMOS switch remains on continuously as long as the current limit is not reached.
Internal Soft-Start Circuit
Soft-start allows a gradual increase of the current-limit level at startup to reduce input surge currents. When the MAX1536 is enabled or powered up, its currentlimit threshold is set to 25% of its final value (25% of 4.8A = 1.2A). The current-limit threshold is increased by 25% every 256 LX cycles. The current-limit threshold reaches its final level of 4.8A after 768 LX cycles or when the output voltage is in regulation, whichever occurs first. Additionally, when VFB < 0.3 x VREFIN, the PMOS switch remains off for the extended off-time of 4 x tOFF. As a result of this soft-start feature, the main output capacitor charges up relatively slowly. The exact time of the output rise depends on the nominal switching frequency, output capacitance, and the load current. See the startup waveforms in the Typical Operating Characteristics.
Short-Circuit/Overload Protection
The MAX1536 can sustain a constant short circuit or overload. Under a short-circuit or overload condition, when V FB < 0.3 x V REFIN , the MAX1536 uses an
9
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3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
L1 1.2H, SUMIDA CDR7D28MN-1R2 VIN +3.0V TO +5.5V 10 CIN 2 X 10F +6.3V X5R IN LX RA VCC COMP PGOOD FB PGND AGND RB COUT 100F, +6.3V POSCAP VOUT +0.7V TO VIN
2.2F 100k POWER GOOD
CCOMP 470pF
REF PWM MODE IDLE MODE REFIN ON OFF OD FBLANK OD R3 R VOUT = VFB 1 + A RB VFB(LOW) = VREF R2 R1 + R2 SHDN R2 CREFIN 470pF
MAX1536
SKIP R1
CREF 0.22F
TOFF RTOFF 75k
GATE VFB(HIGH)
VFB(LOW)
VFB(HIGH) = VREF
() () ( )
R2 + R3 R1 + R2 + R3
Figure 1. MAX1536 Standard Application Circuit
Table 1. Recommended Component Values (IOUT = 3.6A)
VIN (V) 5 5 5 5 3.3 3.3 3.3 VOUT (V) 3.3* 2.5* 1.8/1.5** 0.7* 2.5* 1.8/1.5** 0.7* FULL-LOAD SWITCHING FREQUENCY fPWM (kHz) 1020 1020 820/900 450 640 840/1030 660 L (H) 1.2 1.2 1.2 1.2 1.0 1.0 1.0 RTOFF (k) 30.1 47.5 78.7 200 30.1 49.9 121 R1 (k) Short Short 20 130 Short 20 130 R2 (k) Open Open 60.4 69.8 Open 60.4 69.8 R3 (k) Open Open 121 Short Open 121 Short RA (k) 6.49 2.49 Short Short 2.49 Short Short RB (k) 10 10 Open Open 10 Open Open
*In single-output voltage applications, OD, OD, and GATE are general-purpose gates. If OD and OD are not used, connect GATE to AGND and leave OD and OD open. **The output voltage changes between two set points depending on VGATE. See the Setting Dynamic Output Voltages with REFIN section.
10
______________________________________________________________________________________
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Table 2. Component Manufacturers
SUPPLIER Coilcraft Coiltronics Kemet Sanyo Sumida Taiyo Yuden TDK TOKO COMPONENT Inductors Inductors Capacitors Capacitors Inductors Capacitors Capacitors Inductors PHONE 800-322-2645 (USA) 561-752-5000 (USA) 408-986-0424 (USA) 818-998-7322 (USA) 408-982-9660 (USA) 03-3667-3408 (Japan), 408-573-4150 (USA) 847-803-6100 (USA), 81-3-5201-7241 (Japan) 858-675-8013 (USA) WEBSITE www.coilcraft.com www.coiltronics.com www.kemet.com www.sanyo.com www.sumida.com www.t-yuden.com www.component.tdk.com www.toko.com
VCC PGOOD REF PGOOD COMPARATOR REFIN Gm SUMMING COMPARATOR CURRENT SENSE IN CIN VIN COMP SHDN VCC
VIN +3.0V TO +5.5V
MAX1536
*FB
OD
FB OD FBLANK DECODE AND TIMER 2.0V REF TIMER
PWM LOGIC AND DRIVERS
LX
L
VOUT +0.7V TO VIN
COUT CURRENT SENSE
PGND
GATE FBLANK REF
AGND
TOFF
SKIP *FOR VOUT > 2.0V, USE AN FB RESISTIVE DIVIDER *FROM VOUT TO AGND.
Figure 2. MAX1536 Functional Diagram
extended off-time to control the current. Operation during a short-circuit or overload is similar to forced-PWM mode except the off-time is 4 x tOFF. At the end of each off-time, the PMOS switch turns on and remains on until the output is in regulation or the current through the switch increases to the 4.8A current limit. When the PMOS switch turns off, it remains off for four times the programmed off-time (tOFF), and the NMOS synchro-
nous switch turns on. Since either the NMOS or the PMOS switch is always on, the inductor current is continuous. The RMS inductor current during a short circuit remains below the 4.8A current-limit threshold. The MAX1536 operates using the extended off-time until the short-circuit or overload is removed and VFB > 0.3 x VREFIN. Prolonged short circuit or overload can result in thermal shutdown.
______________________________________________________________________________________
11
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Shutdown (SHDN)
Drive SHDN low to disable the MAX1536 and reduce the supply current to less than 1A. In shutdown, all circuitry and internal MOSFETs turn off, and the LX node becomes high impedance. Drive SHDN high or connect to VCC for normal operation.
Table 3. FBLANK Configuration Table
FBLANK VCC Open REF AGND FAULT BLANKING Enabled Enabled Enabled Disabled TYPICAL FORCED-PWM DURATION (s) 150 100 50 100
Summing Comparator
Three signals are added together at the input of the summing comparator (Figure 2): an output-voltage error signal relative to the reference voltage, an integrated output-voltage error signal, and the sensed PMOS switch current. The transconductance amplifier with an external capacitor between COMP and V CC provides an integrated error signal. This integrator provides high DC accuracy without the need for a highgain amplifier (see the Integrator Amplifier section).
Fault Blanking (FBLANK)
The MAX1536 automatically enters forced-PWM operation for a predefined period following any GATE transition. The FBLANK control input determines how long the MAX1536 maintains forced-PWM operation (Table 3). When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1536 forces PGOOD to a high-impedance state during the transition period selected by FBLANK (Table 3). This prevents the PGOOD signal from going low when the output-voltage change (VOUT) cannot occur as fast as the change in REFIN voltage (VREFIN).
Power-Good Output (PGOOD)
PGOOD is an open-drain output that indicates if the output voltage is in regulation. PGOOD is actively held low in shutdown and during soft-start. After the softstart terminates, PGOOD becomes high impedance as long as the output voltage is within 10% of the nominal regulation voltage. Once the MAX1536 has started, PGOOD pulls low when the output voltage drops 10% below or rises 10% above the nominal regulation voltage. PGOOD returns to high impedance when the output voltage regains regulation. For logic-level output voltages, connect a 100k external pullup resistor between PGOOD and VCC. PGOOD is forced high impedance during the transition period selected by FBLANK (see the Fault Blanking section).
Synchronous Rectification
In a nonsynchronous step-down regulator, an external Schottky diode provides a path for current to flow when the inductor is discharging. The MAX1536 synchronous rectifier replaces the external Schottky diode with an internal low-resistance NMOS switch reducing conduction losses and improving efficiency (Figure 3). There is typically 40ns of delay between MOSFET transitions, thus preventing cross conduction or "shoot through."
NONSYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR VIN VIN CIN
CIN
L L VOUT COUT COUT VOUT
SYNCHRONOUS RECTIFIER
Figure 3. Step-Down Switching Regulator 12 ______________________________________________________________________________________
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
Thermal Shutdown
The MAX1536 features a thermal fault-protection circuit. When the junction temperature rises above +165C, a thermal sensor shuts down the MAX1536 regardless of V SHDN. The MAX1536 is reactivated after the junction temperature cools to +150C. Junction-to-ambient thermal resistance, JA, is highly dependent on the amount of copper area connected to the exposed backside pad. Airflow over the board significantly reduces JA. For heat-sinking purposes, evenly distribute the copper area connected at the IC among the high-current pins. Refer to the Maxim website (www.maxim-ic.com) for QFN thermal considerations. The junction-to-ambient thermal resistance required to dissipate this amount of power is calculated by: JA TJ(MAX) - TA(MAX) PSL + PCL
MAX1536
Thermal Resistance
where: JA = junction-to-ambient thermal resistance. TJ(MAX) = maximum junction temperature = +150C. TA(MAX) = maximum ambient temperature.
Design Procedure
For typical applications, use the recommended component values in Table 1. For other applications, take the following steps: 1) Select the desired PWM-mode switching frequency. See Figure 4 for maximum operating frequency. 2) Select the constant off-time as a function of input voltage, output voltage, and switching frequency. 3) Select RTOFF as a function of off-time. 4) Select the inductor as a function of output voltage, off-time, and peak-to-peak inductor current.
Power Dissipation
Power dissipation in the MAX1536 is dominated by conduction losses in the two internal power switches. Power dissipation due to supply current in the control section and average current used to charge and discharge the gate capacitance of the internal switches (i.e., switching losses--PSL) is approximately: PSL = C x VIN2 x fSW where: C = 5nF. fSW = switching frequency. The combined conduction losses (P CL ) in the two power switches are approximated by: PCL = IOUT2 x RPMOS where: IOUT = load current. RPMOS = PMOS switch on-resistance.
1800 1600 1400 FREQUENCY (kHz) 1200 1000 800 600 400 200 0 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 VOUT = 3.3V NO LOAD VOUT = 2.5V VOUT = 1.0V
Setting the Output Voltage
Setting VOUT with a Resistive Voltage-Divider at FB The MAX1536 output voltage (VOUT) is set using FB and REFIN (Figure 5). The MAX1536 regulates VFB to be equal to VREFIN. Connect FB to a resistive voltagedivider between VOUT and AGND to adjust VOUT from +0.7V to VIN. Select an RB from 10k to 100k, then calculate RA based on the desired VOUT:
VOUT = 1.5V VOUT = 1.8V
RA VOUT = VFB 1 + RB
()
MAX1536
VOUT = +2.5V LX PGND VFB = VREFIN RB 10k AGND RA 2.49k
FB
VREF = +2.0V REF CREF 0.22F REFIN
Figure 4. Maximum Recommended Operating Frequency vs. Input Voltage
Figure 5. Setting VOUT with a Resistive Voltage-Divider at FB
______________________________________________________________________________________
13
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
VOUT RA = RB -1 VFB where VFB = VREFIN. Setting Dynamic Output Voltages with REFIN The MAX1536 regulates VFB to be equal to VREFIN. Changing VREFIN allows for a dynamic output voltage that changes between two set points (see the Multioutput Voltage Settings section for information on three or more output-voltage set points). Figure 1 shows a dynamically adjustable resistive voltage-divider network at REFIN. Keep VREFIN between 0.7V and 2V. Keep VREFIN below VCC - 1.35V to avoid an undervoltage lockout condition. Toggling GATE switches in and out the resistor connected between OD and AGND changing VREFIN. A logic high on GATE turns on the internal N-channel MOSFET, forcing OD to a low-impedance state. A low logic on GATE turns off the internal Nchannel MOSFET, making OD high impedance. The output voltage is determined by the following equations: RA VOUT = VFB 1 + RB R2 VFB(LOW ) = VREF R1 + R2 R2 + R3 VFB(HIGH) = VREF R1 + R2 + R3 The MAX1536 automatically enters forced-PWM operation on the rising and falling edges of GATE, and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 3). Forced-PWM operation is required to ensure fast, accurate negative voltage transitions when REFIN is lowered. Since forced-PWM operation disables the zero-crossing comparator, the inductor current can reverse under light loads, quickly discharging the output capacitors. The MAX1536 also forces PGOOD to a high-impedance state for the period selected by FBLANK (Table 3). For a step-voltage change at REFIN, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The voltage across the inductor and the inductance limits the inductor current ramp. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows down the output voltage change during a positive REFIN voltage change, and speeds up the output voltage change during a negative REFIN voltage change. Adding a capacitor across REFIN and AGND filters noise and controls the rate of change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant given by the equivalent parallel resistance seen by the slew capacitor CREFIN. As shown in Figure 1, the time constant for a positive REFIN voltage transition is: R1 x (R2 + R3) POS = CREFIN R1 + R2 + R3 and the time constant for a negative REFIN voltage transition is: NEG = R1 x R2 CREFIN R1 + R2 During a negative REFIN voltage transition, the MAX1536 sinks current to discharge the output capacitor and bring the output voltage down to the new set point. The MAX1536 does not have a negative current limit, so NEG must be set long enough to keep the sinking current within the maximum current capability of the IC: NEG COUT x VOUT and ISINK ILIMIT ISINK
MAX1536
Programming the No-Load Switching Frequency and Off-Time
The MAX1536 features a programmable PWM mode switching frequency, which is set by the input and output voltage and the value of RTOFF. RTOFF sets the PMOS power switch off-time in PWM mode. Use the following equation to select the off-time according to the desired no-load switching frequency in PWM mode: tOFF = where: tOFF = the programmed off-time. VIN = the input voltage. VOUT = the output voltage. fPWM = no-load switching frequency, PWM mode. Select RTOFF according to the formula: VIN - VOUT fPWM x VIN
14
______________________________________________________________________________________
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
RTOFF = (tOFF - 0.07s) 110k 1.00s The peak-inductor current at full load is 1.125 x IOUT if the above equation is used; otherwise, the peak current is calculated by: IPEAK = IOUT + VOUT x tOFF 2 xL
MAX1536
VTOFF is typically 1.1V and the recommended values for RTOFF range from 30.1k to 499k for off-times of 0.3s to 4.5s.
Frequency Variation with Output Current
The operating frequency of the MAX1536 in PWM mode is determined primarily by tOFF (set by RTOFF), VIN, and VOUT as shown in the following formula: VIN - VOUT - VPMOS fPWM = tOFF (VIN - VPMOS + VNMOS) where: VPMOS = the voltage drop across the internal PMOS power switch, IOUT x RPMOS. VNMOS = the voltage drop across the internal NMOS synchronous-rectifier switch, IOUT x RNMOS. As the output current increases, V NMOS and VPMOS increase and the voltage across the inductor decreases. This causes the frequency to drop. Approximate the change in frequency with the following formula: fPWM = IOUT x RPMOS VIN x tOFF
Choose an inductor with a saturation current at least as high as the peak-inductor current. The inductor selected should exhibit low losses at the chosen operating frequency.
Capacitor Selection
The input-filter capacitor reduces peak currents and noise at the voltage source. Use a low-ESR and lowESL capacitor located no further than 5mm from IN. Select the input capacitor according to the RMS input ripple-current requirements and voltage rating: IRIPPLE = ILOAD VOUT (VIN - VOUT) VIN
where IRIPPLE = input RMS current ripple. The output-filter capacitor affects the output-voltage ripple, output load-transient response, and feedbackloop stability. For stable operation, the MAX1536 requires a minimum output ripple voltage of VRIPPLE 1% x VOUT. The minimum ESR of the output capacitor is calculated by: ESR >1% x L tOFF
where RPMOS is the resistance of the internal MOSFETs (54m, typ).
Inductor Selection
The key inductor parameters must be specified: inductor value (L) and peak current (IPEAK). The following equation includes a constant, denoted as LIR, which is the ratio of peak-to-peak inductor AC ripple current to maximum DC load current. A higher value of LIR allows smaller inductance but results in higher losses and ripple. A good compromise between size and losses is found at approximately a 25% ripple-current to loadcurrent ratio (LIR = 0.25), which corresponds to a peakinductor current 1.125 times the DC load current: L= VOUT x tOFF IOUT x LIR Stable operation requires the correct output-filter capacitor. When choosing the output capacitor, ensure that: COUT tOFF 79F x 1V x 1s VOUT
Integrator Amplifier
An internal transconductance amplifier fine tunes the output DC accuracy. A capacitor, CCOMP, from COMP to VCC compensates the transconductance amplifier. For stability, choose CCOMP = 470pF. A larger capacitor value maintains a constant average output voltage, but slows the loop response to changes in output voltage. A smaller capacitor value speeds up the loop response to changes in output voltage but decreases stability.
where: IOUT = maximum DC load current. LIR = ratio of peak-to-peak AC inductor current to DC load current, typically 0.25.
______________________________________________________________________________________
15
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Applications Information
Multioutput Voltage Settings
The MAX1536 is optimized to work in applications that require two dynamic output voltages; however, discrete logic or a DAC connected to REFIN allows three or more dynamic output voltages. Figure 6 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN. An edge-detection circuit is added to trigger a 1s pulse on GATE to start the fault-blanking and forced-PWM operation. GATE requires a minimum pulse width of 500ns. The edge-detection circuit is not required if the MAX1536 is always in PWM mode (SKIP = VCC) and fault blanking is not necessary.
Circuit Layout and Grounding
Good layout is necessary to achieve the intended output power level, high efficiency, and low noise. Good layout includes the use of a ground plane, careful component placement, and correct routing of traces using appropriate trace widths. Refer to the MAX1536 EV Kit for layout reference.
VCC VDDQ SKIP IN CIN 1000pF 10k VIN
MAX1536
REFIN
FB L LX VTT = VDDQ 2
Active Bus Termination
Active bus termination power supplies generate a voltage rail that tracks a set reference. Active bus termination power supplies are unique because they source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the MAX1536 to generate the termination voltage using a resistor-divider at REFIN. Force the MAX1536 to operate in PWM mode (SKIP = VCC) to source and sink current. Figure 7 shows the MAX1536 configured as a DDR termination regulator. Connect GATE and FBLANK to AGND when unused.
R4 REF R1 B R3 REFIN A C1 R2
1000pF
10k AGND PGND OD OD GATE FBLANK
COUT
VDDQ = DDR MEMORY SUPPLY VOLTAGE VTT = TERMINATION SUPPLY VOLTAGE
Figure 7. Active Bus Termination
MAX1536
AGND
VOUT 50mV/div VLX 5V/div ILX 2A/div
1.5k 1000pF
OD OD GATE
0
0
1.5k 1000pF
10s/div VIN = 3.3V, VOUT = 1.25V, IOUT = -1A TO +1A TO -1A
Figure 6. Multioutput Voltage Settings 16
Figure 8. Source/Sink Waveforms
______________________________________________________________________________________
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
The following points are in order of decreasing importance: 1) Minimize switched-current and high-current ground loops. Connect the input capacitor's ground, the output capacitor's ground, and PGND at a single point. Connect the resulting island to AGND at only one point. 2) Connect the input filter capacitor less than 5mm away from IN. The connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 3) Place the LX node components as close together and as near to the device as possible. This reduces noise, resistive losses, and switching losses. 4) A ground plane is essential for optimal performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more layers is recommended. Use the top and bottom layers for interconnections and the inner layers for an uninterrupted ground plane. Avoid large AC currents through the ground plane.
MAX1536
Chip Information
TRANSISTOR COUNT: 4305 PROCESS: BiCMOS
______________________________________________________________________________________
17
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control MAX1536
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L
C L
b D2/2
0.10 M C A B
XXXXX
E/2 E2/2 E (NE-1) X e
C L
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
1 2
18
______________________________________________________________________________________
QFN THIN.EPS
3.6A, 1.4MHz, Low-Voltage, Internal-Switch StepDown Regulator with Dynamic Output Voltage Control
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1536
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 T4055-1
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
A A1 A3 b D E e k L
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.25 - 0.25 0.20 REF. 0.20 REF. 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.50 BSC. - 0.25 0.25 0.20 REF. 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 0.40 BSC. 0.25 0.35 0.45
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** **
NO YES NO NO YES NO YES NO NO YES YES NO NO YES YES NO NO YES NO NO YES
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 20 28 32 N 40 ND 4 5 7 8 10 4 5 7 8 10 NE WHHB WHHC WHHD-1 WHHD-2 ----JEDEC L1
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
3.30 3.40 3.20
** SEE COMMON DIMENSIONS TABLE
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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